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low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 1 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer g eneral d escription the ics853006 is a low skew, high performance 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer and a member of the hiperclock s ? family of high performance clock solutions from ics. the ics853006 is characterized to operate from a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ics853006 ideal for those applications demanding well defined performance and repeatability. f eatures ? 6 differential lvpecl outputs ? 1 differential pclk, npclk input pair ? pclk, npclk pair can accept the following differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: > 2ghz ? output skew: 30ps (maximum) ? part-to-part skew: 150ps (maximum) ? propagation delay: 510ps (maximum) ? jitter, rms: < 0.03ps (typical) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.465v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -2.375v to -3.465v ? lead-free package available ? -40c to 85c ambient operating temperature b lock d iagram p in a ssignment v cc nq0 q0 nq1 q1 nq2 q2 v cc pclk npclk 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc q5 nq5 q4 nq4 q3 nq3 vcc v ee v bb hiperclocks? ics ics853006 20-lead tssop 6.5mm x 4.4mm x 0.92mm package body g package top view pclk npclk q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 v bb idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 1 data sheet ics853006
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 2 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 2 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. c lock i nput f unction t able l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 7k ? r 2 / c c v r o t s i s e r n w o d l l u p / p u l l u p t u p n i 0 5k ? t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l c pk l c p n5 q : 0 q5 q n : 0 q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n r e b m u ne m a ne p y tn o i t p i r c s e d 0 2 , 3 1 , 8 , 1v c c r e w o p. s n i p y l p p u s e v i t i s o p 3 , 20 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 , 41 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 , 62 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9k l c pt u p n in w o d l l u p. t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i - n o n 0 1k l c p nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l c e p v l l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 1 1v b b t u p t u o. e g a t l o v s a i b 2 1v e e r e w o p. n i p y l p p u s e v i t a g e n 5 1 , 4 13 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 1 , 6 14 q , 4 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 1 , 8 15 q , 5 q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 3 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 3 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v cc = 2.375v to 3.465v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 23 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 1 1a m t able 4b. lvpecl dc c haracteristics , v cc = 3.3v; v ee = 0v a bsolute m aximum r atings supply voltage, v cc 4.6v (lvpecl mode, v ee = 0) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5 v inputs, v i (ecl mode) 0.5v to v ee - 0.5v outputs, i o continuous current 50ma surge current 100ma v bb sink/source, i bb 0.5ma operating temperature range , ta -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 73.2c/w (0 lfpm) (junction-to-ambient) note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 1 . 25 7 2 . 28 3 . 25 2 2 . 25 9 2 . 27 3 . 25 9 2 . 23 3 . 25 6 3 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 4 . 15 4 5 . 18 6 . 15 2 4 . 12 5 . 15 1 6 . 14 4 . 15 3 5 . 13 6 . 1v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 0 . 26 3 . 25 7 0 . 26 3 . 25 7 0 . 26 3 . 2v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 4 . 15 6 7 . 13 4 . 15 6 7 . 13 4 . 15 6 7 . 1v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 6 8 . 18 9 . 16 8 . 18 9 . 16 8 . 18 9 . 1v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c 2 . 13 . 32 . 13 . 32 . 13 . 3v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p 0 1 -0 1 - 0 1 - a k l c p n 0 5 1 -0 5 1 - 0 5 1 - a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n c c . v 3 . 0 +
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 4 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 4 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t able 4c. lvpecl dc c haracteristics , v cc = 2.5v; v ee = 0v t able 4d. ecl dc c haracteristics , v cc = 0v; v ee = -3.465v to -2.375v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 3 . 15 7 4 . 18 5 . 15 2 4 . 15 9 4 . 17 5 . 15 9 4 . 13 5 . 15 6 5 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 6 . 05 4 7 . 08 8 . 05 2 6 . 02 7 . 05 1 8 . 04 6 . 05 3 7 . 03 8 . 0v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 2 . 16 5 . 15 7 2 . 16 5 . 15 7 2 . 1 3 8 . 0 - v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 6 . 05 6 9 . 03 6 . 05 6 9 . 03 6 . 05 6 9 . 0v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c 2 . 15 . 22 . 15 . 22 . 15 . 2v i h i t u p n i t n e r r u c h g i h k l c p n , 0 k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p 0 1 -0 1 -0 1 -a k l c p n 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 2 1 . 1 -5 2 0 . 1 -2 9 . 0 -5 7 0 . 1 -5 0 0 . 1 -3 9 . 0 -5 0 0 . 1 -7 9 . 0 -5 3 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 9 8 . 1 -5 5 7 . 1 -2 6 . 1 -5 7 8 . 1 -8 7 . 1 -5 8 6 . 1 -6 8 . 1 -5 6 7 . 1 -7 6 . 1 -v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c v e e v 2 . 1 +0v e e v 2 . 1 +0v e e v 2 . 1 +0v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p 0 1 -0 1 -0 1 -a k l c p n 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n c c . v 3 . 0 +
853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 5 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t able 5. ac c haracteristics , v cc = 0v; v ee = -2.375v to -3.465v or v cc = 2.375 to 3.465v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m f x a m y c n e u q e r f t u p t u o2 >2 >2 >z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p0 4 30 0 40 6 40 5 30 1 40 7 40 9 30 5 40 1 5s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o5 17 25 17 27 10 3s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p0 5 10 5 10 5 1s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r 3 0 . 03 0 . 03 0 . 0s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 90 5 15 0 25 90 5 15 0 25 90 5 15 0 2s p d e r u s a e m e r a s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u z h g 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 5 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 6 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 6 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer a dditive p hase j itter input/output additive phase jitter at 155.52mhz = 0.03ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m the spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in as with most timing specifications, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the de- the 1hz band to the power in the fundamental. when the re- quired offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the funda- mental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 7 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer p arameter m easurement i nformation o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew p art - to -p art s kew o utput r ise /f all t ime p ropagation d elay v cmr cross points v pp v ee npclk v cc pclk scope qx nqx lvpecl 2v t sk(pp) t sk(o) nqx qx nqy qy pa r t 1 pa r t 2 nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v swing t pd npclk q0:q5 nq0:nq5 pclk v cc v ee -0.375v to -1.465v idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 7
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 8 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 8 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer a pplication i nformation figure 1 shows an example of the differential input that can be wired to accept single ended levels. the reference voltage level v bb generated from the device is connected to the negative input. f igure 1. s ingle e nded s ignal d riving d ifferential i nput v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination w iring the d ifferential i nput to a ccept s ingle e nded l evels the c1 capacitor should be located as close as possible to the input pin. pclk npclk vbb c1 0.1u clk_in vcc
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 9 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 9 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t ermination for 2.5v lvpecl o utput figure 3a and figure 3b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminat- ing 50 ? to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 3b can be eliminated and the termination is shown in figure 3c. f igure 3c. 2.5v lvpecl t ermination e xample f igure 3b. 2.5v lvpecl d river t ermination e xample f igure 3a. 2.5v lvpecl d river t ermination e xample r2 62.5 zo = 50 ohm r1 250 + - 2.5v 2,5v lvpecl driv er r4 62.5 r3 250 zo = 50 ohm 2.5v vcc=2.5v r1 50 r3 18 zo = 50 ohm zo = 50 ohm + - 2,5v lvpecl driv er vcc=2.5v 2.5v r2 50 2,5v lvpecl driv er vcc=2.5v r1 50 r2 50 2.5v zo = 50 ohm zo = 50 ohm + -
853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 10 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver ter- mination requirements. f igure 4a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 4b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 4c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 4f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 4e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm f igure 4d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm r2 50 zo = 50 ohm c1 r1 50 c2 pclk/npclk r5 100 - 200 zo = 50 ohm r6 100 - 200 pclk npclk vbb 3.3v lvpecl 3.3v 3.3v lvds 3.3v zo = 50 ohm 3.3v pclk npclk vbb r2 1k c2 r1 1k r5 100 c1 pclk/npclk zo = 50 ohm idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 10 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 11 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 11 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer f igure 5. ics853006 lvpecl c lock o utput b uffer s chematic e xample s chematic e xample figure 5 shows a schematic example of ics853006. the ics853006 input can accept various types of differential input signal. in this example, the inputs are driven by an lvpecl driv- ers. for the ics853006 lvpecl output driver, an example of lvpecl driver termination approach is shown in this schematic. zo = 50 r10 50 + - 3.3v zo = 50 r11 50 zo = 50 zo = 50 r6 50 c5 (optional) 0.1u (u1, 20) r5 50 3.3v r3 50 3.3v lvpecl c1 0.1u c2 0.1u c6 (optional) 0.1u c3 0.1u r2 50 3.3v 3.3v (u1, 13) (u1, 1) c4 0.1u zo = 50 r4 50 (u1, 8) r1 50 zo = 50 r9 50 c7(optional) 0.1u u1 ics853006 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 vcc nq0 q0 nq1 q1 nq2 q2 vcc pclk npclk vbb vee vcc nq3 q3 nq4 vcc q5 nq5 q4 + - additional lvpecl driver termination approaches are shown in the lvpecl termination application note. it is recommended at least one decoupling capacitor per power pin. the decoupling capacitors should be physically located near the power pins. for ics853006, the unused output can be left floating.
853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 12 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics853006. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics853006 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 115ma = 398.48mw ? power (outputs) max = 30.94mw/loaded output pair if all outputs are loaded, the total power is 6 * 30.94mw = 185.64mw total power _max (3.465v, with all outputs switching) = 398.48mw + 185.64mw = 584.12mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used . assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.584w * 66.6c/w = 123.9c. this is below the limit of 125c this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 20- pin tssop, f orced c onvection idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 12 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd
idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 13 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 13 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. for logic high, v out = v oh_max = v cc_max ? 0.935v (v cc_max - v oh_max ) = 0.935v for logic low, v out = v ol_max = v cc_max ? 1.67v (v cc_max - v ol_max ) = 1.67v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.935v)/50 ? ] * 0.935v = 19.92mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.67v)/50 ? ] * 1.67v = 11.02mw total power dissipation per output pair = pd_h + pd_l = 30.94mw f igure 6. lvpecl d river c ircuit and t ermination vout q1 vcc - 2v rl 50 vcc
ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 14 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics853006 is: 1340 t able 7. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 14
853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 15 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n0 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 4 . 60 6 . 6 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0 idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 15 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd
ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd 853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 16 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t g a 6 0 0 3 5 8 s c ig a 6 0 0 3 5 8 s c ip o s s t d a e l 0 2e b u t r e p 2 7c 5 8 o t c 0 4 - t g a 6 0 0 3 5 8 s c ig a 6 0 0 3 5 8 s c il e e r d n a e p a t n o p o s s t d a e l 0 20 0 5 2c 5 8 o t c 0 4 - f l g a 6 0 0 3 5 8 s c il g a 6 0 0 3 5 8 s c ip o s s t " e e r f - d a e l " d a e l 0 2e b u t r e p 2 7c 5 8 o t c 0 4 - t f l g a 6 0 0 3 5 8 s c il g a 6 0 0 3 5 8 s c i n o p o s s t " e e r f - d a e l " d a e l 0 2 l e e r d n a e p a t 0 0 5 2c 5 8 o t c 0 4 - the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries. idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 16
853006ag www.icst.com/products/hiperclocks.html rev. a november 9, 2004 17 integrated circuit systems, inc. ics853006 l ow s kew , 1- to -6 d ifferential - to -2.5v/3.3v lvpecl/ecl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 8 t 1 6 1 . n o i t c e s s e r u t a e f o t t e l l u b e e r f - d a e l d e d d a . e l b a t n o i t a m r o f n i g n i r e d r o o t n / p e e r f - d a e l d e d d a 4 0 / 9 / 1 1 idt? / ics? low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer ics853006 17 ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd
ics853006 low skew, 1-to-6 differential-to-2.5v/3.3v lvpecl/ecl fanout buffer tsd ics1893bf 3.3-v 10base-t/100base-tx integrated phyceiver? tsd ics8705 zero delay, differential-to-lvcmos/lvttl clock generator tsd ics1522 user-programmable video clock generator/ line-locked clock regenerator tsd ics9148-82 frequency generator & integrated buffers for pentium/pro? tsd ics8535-01 low skew, 1-to-4 lvcmos/lvttl-to-3.3v lvpecl fanout buffer tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com ics8521 low skew, 1-to-9 differentia l-to-hstl fanout buffer tsd

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